Recently, digital television sets and other digital electric appliances are conquering the general household. The popularity of digital electric household appliances depends on high performance and multiple functions of the products.
The performance of digital electric household appliances is enhanced by increasing the speed of digital signal processing. The enhancement of speed of digital signal processing is realized by increase of clock frequency of system LSI, extension of data bus width, and use of high-speed memory such as DDR (double data rate) memory.
To increase the functions of digital electric household appliances, higher integration of circuits is needed. The integration of circuits may be enhanced by assembling a plurality of electronic components in one package by the technology of, for example, MCM (multi-chip module), SIP (system-in-package), or POP (package-on-package).
With an advanced integration of a circuit, multiple functions can be incorporated in a product, but the number of interface signals for operating the functions also increases. As a result, the number of external terminals provided outside of the package increases. In addition, along with the increase in the number of electronic components contained in the package, the number of external terminals for their inspection increases. Such package is connected electrically to the external board through external terminals, but the number of external terminals increases, and the package increases in size. The board of a digital electric household appliance for mounting the package increases in size as the package size increases, and the digital electric household appliance itself increases in size.
In the IC package in patent document 1, a lower stage lead wire is provided in a first layer of a two-layer lead board, and an upper stage lead terminal is provided in a second layer as a terminal for test. In this configuration, the upper stage lead terminal provided in the second layer of the lead board is not connected to the circuit board. That is, the terminal for test is provided in the second layer of the lead board, and the number of terminals provided in a region connected to the circuit board (the first layer of the lead board) is curtailed. As a result, the size of the IC package is reduced.
When inspecting and shipping the electronic components contained in the package, they are generally inspected after the package assembly is completed. Hence, generally, the package must be detachably connected to the inspection apparatus. In the socket disclosed in patent document 2, the pin contact opposite to the solder ball in the lower part of BGA package, and the socket contact opposite to this pin contact are contained in the socket main body. Then, the BGA package and the board are detachable.
However, in the configuration of the IC package disclosed in patent document 1, the lead board is formed in two layers for forming the terminal for test. In this case, by forming the board not necessary as the function for the electronic component, the manufacturing cost and the number of manufacturing processes increases.
Besides, since the terminal for test is formed in the lead board of the second layer, the length of the wire for connecting the terminal for test and the IC chip becomes longer. In this case, it is hard to match the impedance between the terminal for test and the IC chip. As a result, when inspecting the IC chip, a reflection wave is generated at the terminal for test or the wire end, and a waveform distortion may be included in the inspection signal. It is hence difficult to inspect the IC chip precisely.
When the socket in patent document 2 and the IC package in patent document 1 are combined, the terminal for test and the pin contact cannot be connected electrically. Hence, the inspection apparatus and the terminal for test cannot be connected, and the electronic component in the inside of the IC package cannot be inspected.    [Patent document 1] Unexamined Japanese Patent Publication No. 2000-68440    [Patent document 2] Unexamined Japanese Patent Publication No. H8-31532